The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
May. 25, 2021
Applicant:
Realtek Semiconductor Corporation, Hsinchu, TW;
Inventor:
Po-Lin Chen, Hsinchu, TW;
Assignee:
REALTEK SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31701 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318594 (2013.01);
Abstract
A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.