The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Aug. 20, 2021
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Davide Argento, Milan, IT;

Orazio Pennisi, Pieve Emanuele, IT;

Stefano Castorina, Milan, IT;

Vanni Poletto, Milan, IT;

Matteo Landini, Bareggio, IT;

Andrea Maino, Novara, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 19/10 (2006.01); H03M 1/12 (2006.01); H03M 3/00 (2006.01); B60R 21/017 (2006.01);
U.S. Cl.
CPC ...
G01R 19/10 (2013.01); B60R 21/0173 (2013.01); H03M 1/124 (2013.01); H03M 3/464 (2013.01); H03M 3/494 (2013.01);
Abstract

A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.


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