The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jan. 04, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Wooyoung Choi, Seoul, KR;

Juseong Oh, Seoul, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H10B 12/00 (2023.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G11C 5/10 (2006.01);
U.S. Cl.
CPC ...
H10B 12/37 (2023.02); G11C 5/10 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 28/60 (2013.01);
Abstract

A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.


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