The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Aug. 31, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Michael Henderson Perrott, Nashua, NH (US);

Robert Karl Butler, Issaquah, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/08 (2006.01); H03L 7/107 (2006.01); H03L 7/081 (2006.01); H03L 7/187 (2006.01); H03L 7/04 (2006.01); G11C 11/4093 (2006.01); G11C 11/4099 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/18 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); G11C 11/4093 (2013.01); G11C 11/4099 (2013.01); H03L 7/04 (2013.01); H03L 7/0816 (2013.01); H03L 7/1072 (2013.01); H03L 7/187 (2013.01); H03M 1/0626 (2013.01); H03M 1/0687 (2013.01); H03M 1/0836 (2013.01); H03M 1/182 (2013.01);
Abstract

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.


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