The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Aug. 28, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Takahisa Kanemura, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H10B 43/40 (2023.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/24 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 29/4234 (2013.01); H01L 29/24 (2013.01); H01L 29/66545 (2013.01); H01L 29/792 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

According to one embodiment, a semiconductor device includes a memory region and a peripheral circuit region, the peripheral circuit region includes a first region and a second region outside of the first region. The semiconductor device includes, in the first region, a transistor including a gate insulating layer and a gate structure that includes a gate electrode. A first structure is in the second region and includes a first insulating layer and a dummy gate electrode on the first insulating layer. The first insulating layer has a side surface facing outward from the peripheral circuit region and a second insulating layer that covers the first side surface and is an insulating material other than a silicon oxide.


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