The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Aug. 31, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Thomas Dyer Bonifield, Dallas, TX (US);

Jeffrey Alan West, Dallas, TX (US);

Byron Lovell Williams, Plano, TX (US);

Elizabeth Costner Stewart, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 23/5223 (2013.01); H01L 27/0292 (2013.01);
Abstract

A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.


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