The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Feb. 24, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Myungsam Kang, Hwaseong-si, KR;

Youngchan Ko, Seoul, KR;

Taesung Jeong, Osan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/3107 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 24/20 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01);
Abstract

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.


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