The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Dec. 22, 2021
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Sunghak Jo, Paju-si, KR;

Seongku Lee, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); G09G 3/3266 (2016.01); G09G 3/3258 (2016.01); G09G 3/3208 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/32 (2013.01); G09G 3/3208 (2013.01); G09G 3/3258 (2013.01); G09G 2310/021 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/00 (2013.01); G09G 2330/02 (2013.01); G09G 2330/12 (2013.01);
Abstract

Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q' node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.


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