The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2023
Filed:
Aug. 29, 2019
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Toru Ido, Edinburgh, GB;
David Paul Singleton, Edinburgh, GB;
Gordon James Bates, Edinburgh, GB;
John Anthony Breslin, Edinburgh, GB;
Cirrus Logic Inc., Austin, TX (US);
Abstract
This application relates to computing circuitry () for analogue computing. A plurality of current generators () are each configured to generate a defined current (I, I, . . . I) based on a respective input data value (D, D, . . . D). A memory array (), having at least one set () of programmable-resistance memory cells (), is arranged to receive the defined currents from each of the current generators at a respective signal line (). Each set () of programmable-resistance memory cells () includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module () is coupled to each of the signal lines to generate a voltage at an output node () based on the sum of the voltages on each of the signal lines.