The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Nov. 04, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Madhu Yashwanth Boenapalli, Hyderabad, IN;

Sai Praneeth Sreeram, Anantapur, IN;

Surendra Paravada, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/084 (2016.01); G06F 12/02 (2006.01); G06F 15/78 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0238 (2013.01); G06F 12/0292 (2013.01); G06F 13/1668 (2013.01); G06F 15/7807 (2013.01); G06F 2212/7201 (2013.01);
Abstract

Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.


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