The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

Jan. 20, 2016
Applicant:

Ultrata, Llc, Vienna, VA (US);

Inventors:

Steven J. Frank, Boulder, CO (US);

Larry Reback, Vienna, VA (US);

Assignee:

Ultrata, LLC, Vienna, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 3/06 (2006.01); H04L 67/1097 (2022.01); G06F 12/0837 (2016.01); G06F 12/0817 (2016.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0613 (2013.01); G06F 3/0631 (2013.01); G06F 3/0632 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 3/0685 (2013.01); G06F 12/0646 (2013.01); G06F 12/0824 (2013.01); G06F 12/0837 (2013.01); H04L 67/1097 (2013.01); G06F 2212/2542 (2013.01);
Abstract

Embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to define arbitrary, parallel functionality such as: direct object address manipulation and generation without the overhead of complex address translation and software layers to manage differing address space; direct object authentication with no runtime overhead that can be set based on secure 3rd party authentication software; object related memory computing in which, as objects move between nodes, the computing can move with them; and parallelism that is dynamically and transparent based on scale and activity. These instructions are divided into three conceptual classes: memory reference including load, store, and special memory fabric instructions; control flow including fork, join, and branches; and execute including arithmetic and comparison instructions.


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