The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Sep. 13, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Teruhisa Sonohara, Yokkaichi Mie, JP;

Shunichi Seno, Yokkaichi Mie, JP;

Hiroki Tokuhira, Kawasaki Kanagawa, JP;

Fumitaka Arai, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); H10B 12/00 (2023.01); H01L 29/786 (2006.01); G11C 11/4076 (2006.01); H01L 29/66 (2006.01); G11C 11/406 (2006.01); G11C 11/4096 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 11/40615 (2013.01); H01L 21/02565 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02);
Abstract

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.


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