The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Aug. 29, 2022
Silanna Asia Pte Ltd, Singapore, SG;
Joseph H. Colles, Bonsall, CA (US);
Steven E. Rosenbaum, San Diego, CA (US);
Stuart B. Molin, Carlsbad, CA (US);
Silanna Asia Pte Ltd, Singapore, SG;
Abstract
In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.