The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Feb. 16, 2021
Applicant:

Alpha and Omega Semiconductor International Lp, Toronto, CA;

Inventors:

David Sheridan, Greensboro, NC (US);

Arash Salemi, Cary, NC (US);

Madhur Bobde, Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 21/0465 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01);
Abstract

A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer.


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