The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Dec. 09, 2021
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventors:
Chiang-Lin Shih, New Taipei, TW;
Pei-Jhen Wu, Taipei, TW;
Ching-Hung Chang, Taoyuan, TW;
Hsih-Yang Chiu, Taoyuan, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/039 (2013.01); H01L 2224/05547 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.