The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Mar. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunkyoung Choi, Hwaseong-si, KR;

Suchang Lee, Seoul, KR;

Yunseok Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/16 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/16 (2013.01); H01L 23/49838 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.


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