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H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H01L 21/76 (2006.01); H01L 23/525 (2006.01); H01L 21/78 (2006.01); H01L 21/82 (2006.01); H01L 23/528 (2006.01); H01L 21/56 (2006.01);

U.S. Cl.

CPC ...

H01L 23/5222 (2013.01); H01L 21/561 (2013.01); H01L 21/76832 (2013.01); H01L 21/78 (2013.01); H01L 21/82 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 24/05 (2013.01); H01L 23/562 (2013.01); H01L 2224/024 (2013.01); H01L 2224/0237 (2013.01);

Abstract

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

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