The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Sep. 01, 2021
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Yoshitaka Ozeki, Tokyo, JP;

Hayato Kurasawa, Tokyo, JP;

Toshinori Uehara, Tokyo, JP;

Koshiro Moriguchi, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06V 40/13 (2022.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G06V 40/1306 (2022.01); G06F 3/0412 (2013.01); H01L 27/1214 (2013.01); H01L 27/1251 (2013.01); H01L 29/42384 (2013.01);
Abstract

A detection device is provided and includes substrate; drive electrode provided on substrate; detection electrode provided on substrate and capacitively coupling with drive electrode; first thin film transistor connected to drive electrode and second thin film transistor connected to first thin film transistor, first insulating film and second insulating film both stacked on substrate, wherein first thin film transistor comprises first gate electrode and first semiconductor layer, second thin film transistor comprises second gate electrode and second semiconductor layer, first semiconductor layer and second semiconductor layer are in same layer and are located between first insulating film and second insulating film, first gate electrode opposes first semiconductor layer via first insulating film, second gate electrode opposes second semiconductor layer via second insulating film, and distance from first gate electrode to first semiconductor layer is greater than distance from second gate electrode to second semiconductor layer.


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