The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Aug. 27, 2019
Samsung Electronics Co., Ltd., Suwon-si, KR;
Ilia Ovsiannikov, Porter Ranch, CA (US);
Ali Shafiee Ardestani, San Jose, CA (US);
Joseph H. Hassoun, Los Gatos, CA (US);
Lei Wang, Burlingame, CA (US);
Sehwan Lee, Hwaseong-si, KR;
JoonHo Song, Hwaseong-si, KR;
Jun-Woo Jang, Hwaseong-si, KR;
Yibing Michelle Wang, Pasadena, CA (US);
Yuecheng Li, San Jose, CA (US);
Samsung Electronics Co., Ltd., Yongin-si, KR;
Abstract
A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.