The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Oct. 04, 2021
Efabless Corporation, San Jose, CA (US);
Bertrand Irissou, San Jose, CA (US);
John M. Hughes, Hartford, CT (US);
Lucio Lanza, Palo Alto, CA (US);
Mohamed K. Kassem, Carlsbad, CA (US);
Michael S. Wishart, Hillsborough, CA (US);
Rajeev Srivastava, Austin, TX (US);
Risto Bell, San Jose, CA (US);
Robert Timothy Edwards, Poolesville, MD (US);
Sherif Eid, Sunnyvale, CA (US);
Greg P. Shaurette, Tahoe City, CA (US);
efabless corporation, San Jose, CA (US);
Abstract
Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.