The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2023
Filed:
Apr. 11, 2022
Amlan Ganguly, W. Henrietta, NY (US);
Sai Manoj Pudukotai Dinakarrao, Falls Church, VA (US);
Mark Connolly, Newfane, NY (US);
Purab Ranjan Sutradhar, Rochester, NY (US);
Sathwika Bavikadi, Fairfax, VA (US);
Mark Allen Indovina, Rochester, NY (US);
Amlan Ganguly, W. Henrietta, NY (US);
Sai Manoj Pudukotai Dinakarrao, Falls Church, VA (US);
Mark Connolly, Newfane, NY (US);
Purab Ranjan Sutradhar, Rochester, NY (US);
Sathwika Bavikadi, Fairfax, VA (US);
Mark Allen Indovina, Rochester, NY (US);
Rochester Institute of Technology, Rochester, NY (US);
Abstract
A processing element includes a PIM cluster configured to read data from and write data to an adjacent DRAM subarray, wherein the PIM cluster has a plurality of processing cores, each processing core of the plurality of processing cores containing a look-up table, and a router connected to each processing core, wherein the router is configured to communicate data among each processing core; and a controller unit configured to communicate with the router, wherein the controller unit contains an executable program of operational decomposition algorithms. The look-up tables can be programmable. A DRAM chip including a plurality of DRAM banks, each DRAM bank having a plurality of interleaved DRAM subarrays and a plurality of the PIM clusters configured to read data from and write data to an adjacent DRAM subarray is disclosed.