The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

May. 13, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghoon Han, Hwaseong-si, KR;

Jongmin Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 23/13 (2013.01); H01L 23/3157 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A semiconductor package includes an upper conductive pattern and a redistribution layer on a first surface of a substrate, a semiconductor chip facing the first surface of the substrate, the semiconductor chip being spaced apart from the first surface of the substrate, a conductive bump bonding between the semiconductor chip and the upper conductive pattern, the conductive bump electrically connecting the semiconductor chip and the upper conductive pattern, and an upper passivation layer on the redistribution layer, a portion of the upper passivation layer facing an edge of a lower surface of the semiconductor chip.


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