The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Apr. 07, 2021
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Shigeki Koya, Nagaokakyo, JP;

Yoshimitsu Takenouchi, Nagaokakyo, JP;

Kenji Sasaki, Nagaokakyo, JP;

Masao Kondo, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/13 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 24/13 (2013.01); H05K 1/0298 (2013.01); H01L 2224/1301 (2013.01); H01L 2224/1308 (2013.01); H01L 2924/14 (2013.01);
Abstract

An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.


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