The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

May. 04, 2022
Applicant:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Inventors:

Benjamin S. Louie, Fremont, CA (US);

Yuniarto Widjaja, Cupertino, CA (US);

Assignee:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/417 (2006.01); G11C 5/14 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 11/412 (2013.01);
Abstract

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.


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