The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Feb. 25, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Yasuhiro Hirashima, Kawasaki Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 8/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/1057 (2013.01); G11C 8/06 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.


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