The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2023
Filed:
Jun. 29, 2021
Applicant:
Amazon Technologies, Inc., Seattle, WA (US);
Inventors:
Uri Leder, Lotem, IL;
Ori Ariel, Ma'ale Adumim, IL;
Max Chvalevsky, Mevaseret Zion, IL;
Benzi Denkberg, Etz Efraim, IL;
Guy Nakibly, Kedumim, IL;
Assignee:
Amazon Technologies, Inc., Seattle, WA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/394 (2020.01); G06F 30/331 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/331 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);
Abstract
An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.