The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Jan. 24, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Daisuke Hashimoto, Cupertino, CA (US);

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 5/14 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 1/266 (2013.01); G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/067 (2013.01); G06F 3/0614 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0683 (2013.01); G06F 3/0688 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G11C 5/144 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 29/52 (2013.01); G06F 2212/152 (2013.01); G06F 2212/214 (2013.01); G06F 2212/261 (2013.01); G06F 2212/263 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7211 (2013.01); Y02D 10/00 (2018.01);
Abstract

A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.


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