The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Aug. 06, 2021
Applicant:

Ultrata, Llc, Vienna, VA (US);

Inventors:

Steven J. Frank, Boulder, CO (US);

Larry Reback, Vienna, VA (US);

Assignee:

Ultrata, LLC, Vienna, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H04L 67/1097 (2022.01); G06F 12/0837 (2016.01); G06F 12/0817 (2016.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0613 (2013.01); G06F 3/0631 (2013.01); G06F 3/0632 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 3/0685 (2013.01); G06F 12/0646 (2013.01); G06F 12/0824 (2013.01); G06F 12/0837 (2013.01); H04L 67/1097 (2013.01); G06F 2212/2542 (2013.01);
Abstract

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.


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