The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Mar. 16, 2021
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Viktor Kremin, Lviv, UA;

Oleksandr Pirogov, Lviv, UA;

Vadym Grygorenko, Lviv, UA;

Jens Weber, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); G01R 27/26 (2006.01); H03K 17/96 (2006.01); H03M 3/00 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G01R 27/2605 (2013.01); G06F 3/0418 (2013.01); G06F 3/04166 (2019.05); H03K 17/962 (2013.01); H03M 3/39 (2013.01); G06F 2203/04108 (2013.01); H03K 2217/96074 (2013.01);
Abstract

An apparatus includes a global baseliner circuit coupled with sensing channels of a sensing device. The global baseliner circuit has a signal generator to generate a rectified sinusoidal signal and a square wave having a frequency matching that of an excitation sinusoidal signal, and is to use the square wave to modulate the excitation sinusoidal signal provided at an output of the global baseliner circuit. A channel baseliner circuit is coupled between the global baseliner circuit and a sensing channel and that includes a switched capacitor coupled between the output of the global baseliner circuit and the sensing channel; a sigma-delta modulator coupled with the signal generator and to generate, from the rectified sinusoidal signal, a density-modulated bit stream; and a pair of AND gates to use the density-modulated bit stream and non-overlapping clock signals to generate outputs including density-modulated clock signals sent to switches of the switched capacitor.


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