The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Feb. 25, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyungeun Choi, Suwon-si, KR;

Jong-ho Moon, Seoul, KR;

Han-sik Yoo, Seongnam-si, KR;

Kiseok Lee, Hwaseong-si, KR;

Sung-hwan Jang, Bucheon-si, KR;

Seungjae Jung, Suwon-si, KR;

Euichul Jeong, Yongin-si, KR;

Taehyun An, Seoul, KR;

Sangyeon Han, Suwon-si, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02);
Abstract

A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.


Find Patent Forward Citations

Loading…