The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jan. 05, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Jan Craninckx, Boutersem, BE;

Ewout Martens, Heverlee, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/10 (2006.01); H03M 1/18 (2006.01); H04N 25/75 (2023.01); H03M 1/56 (2006.01); H04N 5/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1215 (2013.01); H03M 1/1023 (2013.01); H03M 1/187 (2013.01); H03M 1/56 (2013.01); H04N 5/06 (2013.01); H04N 25/75 (2023.01); H03M 1/123 (2013.01);
Abstract

Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.


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