The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2023
Filed:
Dec. 02, 2020
Applicant:
Sony Corporation, Tokyo, JP;
Inventors:
Assignee:
SONY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H04N 23/00 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14612 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14645 (2013.01); H01L 27/14687 (2013.01); H04N 23/00 (2023.01); H04N 25/76 (2023.01); H04N 25/79 (2023.01); H01L 2224/11 (2013.01);
Abstract
A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.