The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Jun. 01, 2022
Applicants:

Shanghai Tianma Micro-electronics Co., Ltd., Shanghai, CN;

Shanghai Avic Opto Electronics Co., Ltd., Shanghai, CN;

Inventors:

Feng Qin, Shanghai, CN;

Kerui Xi, Shanghai, CN;

Tingting Cui, Shanghai, CN;

Jie Zhang, Shanghai, CN;

Xuhui Peng, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/561 (2013.01); H01L 23/3121 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/20 (2013.01); H01L 24/81 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/2101 (2013.01); H01L 2924/37001 (2013.01);
Abstract

Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.


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