The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Nov. 12, 2018
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Hideo Komo, Tokyo, JP;

Takeshi Omaru, Tokyo, JP;

Takuya Tsuru, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 23/40 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 25/11 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4012 (2013.01); H01L 23/3107 (2013.01); H01L 23/367 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 25/117 (2013.01); H01L 25/50 (2013.01); H01L 2023/405 (2013.01); H01L 2023/4031 (2013.01); H01L 2023/4068 (2013.01); H01L 2023/4087 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/83895 (2013.01);
Abstract

An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.


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