The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Sep. 06, 2022
Applicant:

Parallels International Gmbh, Schaffhausen, CH;

Inventors:

Evgeny Nikitenko, Moscow, RU;

Alexey Ivanov, Moscow, RU;

Nikolay Dobrovolskiy, Moscow, RU;

Assignee:

Parallels International GmbH, Schaffhausen, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 17/20 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 1/20 (2013.01); G06T 17/20 (2013.01);
Abstract

An example method of hardware-assisted graphics pipeline emulation comprises: computing, based on an input set of graphic primitives, a set of tessellation factors; computing, based on the input set of graphic primitives, a set of points specifying a plurality of patches; computing, based on the set of points, a tessellation count buffer; generating, based on the set of points and the tessellation count buffer, a tessellation offset buffer; performing, using the tessellation offset buffer, a tessellation setup stage; performing, by a graphics processing unit (GPU), a tessellation stage based on the set of tessellation factors, wherein the tessellation stage generates a plurality of output points corresponding to one or more patches of the plurality of patches; and computing, by a domain shader stage, a plurality of vertex positions defined by the plurality of output points.


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