The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Dec. 07, 2020
Applicant:

Netlist, Inc., Irvine, CA (US);

Inventors:

Hyun Lee, Ladera Ranch, CA (US);

Jayesh R. Bhakta, Cerritos, CA (US);

Assignee:

Netlist, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 1/10 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); G11C 16/00 (2006.01); G11C 29/02 (2006.01); G11C 7/20 (2006.01); G11C 8/12 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 1/10 (2013.01); G06F 3/0613 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 13/1642 (2013.01); G06F 13/28 (2013.01); G06F 13/4027 (2013.01); G11C 5/04 (2013.01); G11C 7/1006 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 8/18 (2013.01); G11C 16/00 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H05K 999/99 (2013.01); G11C 7/109 (2013.01); G11C 7/20 (2013.01); G11C 8/12 (2013.01); G11C 2029/0407 (2013.01);
Abstract

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.


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