The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Sep. 30, 2021
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chao-Wei Huang, Hsinchu, TW;

Chen-Hsing Wang, Hsinchu, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0846 (2016.01); H03K 19/173 (2006.01); H03K 19/20 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0238 (2013.01); G06F 12/0846 (2013.01); H03K 19/1737 (2013.01); H03K 19/20 (2013.01); G06F 2212/1021 (2013.01);
Abstract

A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.


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