The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Aug. 05, 2022
Applicant:

Thales, Courbevoie, FR;

Inventor:

Yann Oster, Toulouse, FR;

Assignee:

THALES, Courbevoie, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G01R 31/319 (2006.01); H03K 19/17728 (2020.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0751 (2013.01); G01R 31/3187 (2013.01); G01R 31/31917 (2013.01); G01R 31/318572 (2013.01); G06F 11/1641 (2013.01); H03K 19/17728 (2013.01);
Abstract

A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.


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