The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

Apr. 29, 2022
Applicant:

Lemon Inc., Grand Cayman, KY;

Inventors:

Junmou Zhang, Los Angeles, CA (US);

Dongrong Zhang, Beijing, CN;

Shan Lu, Los Angeles, CA (US);

Jian Wang, Beijing, CN;

Assignee:

Lemon Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 19/25 (2006.01); H03K 3/037 (2006.01); G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
G01R 19/2513 (2013.01); G05F 1/10 (2013.01); H03K 3/037 (2013.01);
Abstract

The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection. The apparatus connected to an integrated circuit power supply network comprises: a power supply voltage detector, comprising: N buffers, wherein an input terminal of a first buffer is connected to a clock signal, and output terminals of other buffers are connected to the input terminal of an adjacent buffer; N latch chains, each of which comprises M latches, wherein a clock input terminal of each latch is connected to a clock signal, a D terminal of a first latch of each latch chain is connected to the output terminal of a corresponding buffer, and Q terminals of other latches are connected to the D terminal of an adjacent latch, wherein M and N are positive integers, the VDD terminal of each latch is connected to an area in an integrated circuit power supply network where a power supply voltage is to be detected, and a grounding terminal of each latch is connected to a ground; and a voltage regulation module connected to the Q terminal of each latch and configured to detect data output of each latch to determine a magnitude of a power supply voltage.


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