The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Mar. 19, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Shinya Arai, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H10B 43/27 (2023.01); G11C 16/04 (2006.01); H01L 49/02 (2006.01); H10B 43/30 (2023.01); G11C 16/26 (2006.01); H10B 41/20 (2023.01); H10B 41/23 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0466 (2013.01); G11C 16/26 (2013.01); H01L 28/00 (2013.01); H01L 29/40117 (2019.08); H10B 43/30 (2023.02); G11C 16/0483 (2013.01); H10B 41/20 (2023.02); H10B 41/23 (2023.02);
Abstract

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.


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