The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Sep. 29, 2021
Applicant:

Mellanox Technologies, Ltd., Yokneam, IL;

Inventors:

Haggai Eran, Yokneam Illit, IL;

Liran Liss, Atzmon, IL;

Yuval Shpigelman, Netanya, IL;

Idan Burstein, Akko, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 61/00 (2022.01); H04L 49/00 (2022.01); H04L 12/40 (2006.01); H04L 49/90 (2022.01);
U.S. Cl.
CPC ...
H04L 49/3072 (2013.01); H04L 12/40071 (2013.01); H04L 49/9042 (2013.01);
Abstract

In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.


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