The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Nov. 08, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Yi-Chieh Huang, Zhubei, TW;

Ying Wei, San Jose, CA (US);

Chung-Ru Wu, Taoyuan, TW;

Bo-Yu Chen, Taichung, TW;

Haiming Tang, Cupertino, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H03L 7/099 (2006.01); H03L 7/091 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0338 (2013.01); H03L 7/091 (2013.01); H03L 7/0998 (2013.01);
Abstract

A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.


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