The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Feb. 18, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyochul Shin, Seoul, KR;

Seungyeob Baek, Yongin-si, KR;

Sungno Lee, Hwaseong-si, KR;

Heechang Hwang, Seoul, KR;

Michael Choi, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03L 7/081 (2006.01); H04B 1/16 (2006.01); H04L 25/03 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1014 (2013.01); H03L 7/0812 (2013.01); H04B 1/16 (2013.01); H04L 1/0071 (2013.01); H04L 25/03012 (2013.01);
Abstract

An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.


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