The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Nov. 04, 2022
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Jun Koyama, Sagamihara, JP;

Masashi Tsubuku, Atsugi, JP;

Kosei Noda, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G09G 3/20 (2006.01); H01L 29/786 (2006.01); G09G 3/36 (2006.01); G09G 3/3233 (2016.01); G09G 3/3291 (2016.01); H03K 19/003 (2006.01); H03K 19/096 (2006.01); G11C 19/28 (2006.01); H03K 17/16 (2006.01); G11C 19/18 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G09G 3/20 (2013.01); G09G 3/2092 (2013.01); G09G 3/3291 (2013.01); G09G 3/36 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01); H03K 17/161 (2013.01); H03K 19/00315 (2013.01); H03K 19/096 (2013.01); G09G 3/3233 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0439 (2013.01); G09G 2300/08 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.


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