The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Oct. 06, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Yoshiaki Asao, Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/161 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0064 (2013.01); H10N 70/20 (2023.02); G11C 2213/79 (2013.01);
Abstract

A variable resistance memory device includes plural first, second, and third conductors, plural memory cells, and a write circuit. Each memory cell is between one first conductor and one third conductor, and includes a first sub memory cell and a second sub memory cell. The first sub memory cell is between the one first conductor and one second conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is between the one second conductor and the one third conductor, and includes a second variable resistance element and a second bidirectional switching element. The write circuit applies a first potential to the first and third conductors of a selected memory cell, a second potential to the second conductor of the selected memory cell, and a third potential to the first and third conductors of non-selected memory cells.


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