The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Sep. 10, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Gang Sik Lee, Icheon-si, KR;

Joo Hyung Chae, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/14 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01); H03L 7/091 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/062 (2013.01); G11C 7/14 (2013.01); H03L 7/0814 (2013.01); H03L 7/091 (2013.01); H03L 7/0992 (2013.01);
Abstract

An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.


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