The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Oct. 20, 2020
Applicant:

Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen, CN;

Inventor:

Yan Li, Shenzhen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 3/00 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/003 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G11C 19/28 (2013.01);
Abstract

A gate driver on array (GOA) circuit and a display panel is provided. The GOA circuit includes a plurality of cascading GOA units. A current stage of the GOA units includes: a pull-up module, a pull-up control circuit unit, and a selection module. The pull-up module includes a first transistor. A source of the first transistor is connected to the selection module, a gate is connected to the pull-up control module through a first node, and a drain is configured to output a scan signal of the current stage. The selection module is configured to receive a first control signal and a second control signal to control the clock signal to transmit to the source of the first transistor.


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