The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Dec. 28, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Albert Shih-Huai Lin, Mountain View, CA (US);

Rambabu Nerukonda, Sunnyvale, CA (US);

Niravkumar Patel, San Jose, CA (US);

Amitava Majumdar, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 30/20 (2020.01); G06F 11/267 (2006.01); G06F 11/27 (2006.01); H01L 25/00 (2006.01); H03K 19/17732 (2020.01); H03K 19/17764 (2020.01); G06F 115/08 (2020.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); H03K 19/17732 (2013.01); H03K 19/17764 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 2115/08 (2020.01); H01L 22/34 (2013.01); H01L 25/00 (2013.01);
Abstract

An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.


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