Emulating scratchpad functionality using caches in processor-based devices

Abstract

Emulating scratchpad functionality using caches in processor-based devices is disclosed. In one aspect, each cache line within a cache of a processor-based device is associated with a corresponding scratchpad indicator indicating whether the corresponding cache line is exempt from the replacement policy used to select a cache line for eviction. Upon receiving data that corresponds to a memory access operation indicated as requiring scratchpad functionality, the cache controller stores the data in a cache line of the cache, and then sets the corresponding scratchpad indicator for the cache line. Subsequently, the cache controller emulates scratchpad functionality by allowing conventional memory read and write operations to be performed on the cache line, but does not apply its replacement policy to that cache line when selecting a cache line as a candidate for eviction. In this manner, the cache line may remain in the cache for use as scratchpad memory by software.