The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Dec. 16, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Ronald Nerlich, Dresden, DE;

Mark Jung, Marzling, DE;

Johann Zipperer, Unterschleißheim, DE;

Dietmar Walther, Eching, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05B 1/03 (2006.01); G06F 9/448 (2018.01); G06F 8/34 (2018.01); G05B 19/045 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4498 (2018.02); G05B 19/045 (2013.01); G06F 8/34 (2013.01);
Abstract

A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.


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